Electrostatic chucks (ESCs) have been utilized in plasma-based or vacuum-based semiconductor processes such as etching, CVD, and ion implantation, etc. for a long time. Capabilities of the ESCs, including non-edge exclusion and wafer temperature control, have proven to be quite valuable in processing semiconductor substrates or wafers, such as silicon wafers. A typical ESC, for example, comprises a dielectric layer positioned over a conductive electrode, wherein the semiconductor wafer is placed on a surface of the ESC (e.g., the wafer is placed on a surface of the dielectric layer). During semiconductor processing (e.g., plasma processing), a clamping voltage is typically applied between the wafer and the electrode, wherein the wafer is clamped against the chuck surface by electrostatic forces. Furthermore, the wafer can be cooled by introducing a gas, such as helium, and applying backpressure between the wafer and the dielectric layer. A temperature of the wafer can then be controlled by adjusting the backpressure between the wafer and the dielectric layer.
Declamping or un-sticking the wafer from the chuck surface, however, is a concern in many ESC applications. For example, after the clamping voltage is turned off, the wafer typically “sticks” to the chuck surface for a considerable amount of time, wherein the wafer cannot be removed by typical wafer lifting mechanisms (e.g., pins extending through the ESC which are operable to lift the wafer from the surface of the dielectric layer). This wafer declamping problem can reduce the throughput of the process. It is believed that the wafer-declamping problem occurs when residual charges induced by the clamping voltage remain on the dielectric layer or on a surface of the wafer, therein leading to an undesirable electric field and clamping force. According to a charge migration model, residual charges are caused by charge migration and accumulation during clamping, wherein the charges accumulate at the dielectric surface and/or wafer backside (e.g., when the wafer surface comprises an insulating layer).
An RC time constant, for example, can be used to characterize the charge/discharge times which correspond to an amount of time typically required to respectively clamp or de-clamp the wafer. This time constant is determined by the product of a volume resistance of the dielectric layer and a gap capacitance between the wafer and dielectric surfaces, i.e.,
                    RC        =                                            R              die                        ⁢                          C              gap                                =                                    ρ              ⁡                              (                dielectric                )                                      ⁢                          ɛ              0                        ⁢                          ɛ              r                        ⁢                                          d                ⁡                                  (                  dielectric                  )                                            gap                                                          (        1        )            where Rdie is the resistance of the dielectric layer, Cgap is the capacitance of the gap between the wafer and the chuck surface, ρ(dielectric) is the volume resistivity of the dielectric layer, ∈0 is the free space permittivity, ∈r is the dielectric constant of the gap, d(dielectric) is the thickness of the dielectric layer, and gap is the distance between the dielectric and wafer surfaces. For example, for a typical flat-plate ESC, if we assume that ρ(dielectric)=1015 Ω-cm, ∈0=8.85×10−14 F/cm, ∈r=1, d(dielectric)=0.2 mm, and gap=3 μm, we find RC=5900 seconds. This is a fairly long charging/discharging time, meaning that if clamping is longer than 5900 seconds, the declamping time will also last approximately 5900 seconds.
A variety of techniques have been previously disclosed for reducing wafer de-clamping problems encountered in the use of ESCs. For example, one conventional technique involves applying a reversal voltage before the wafer is removed from the ESC, therein eliminating a residual attractive force. This reversal voltage, however, is typically 1.5 to 2 times higher than the clamping voltage, and the de-clamping time is still typically quite large. Another conventional technique involves providing a low-frequency sinusoidal AC voltage in order to produce sine wave fields of controlled amplitude and phase. Such low-frequency sinusoidal AC voltages, however, typically provide low clamping forces, as well as fairly long residual clamping times.
Johnsen-Rahbek (J-R) effect-type ESCs have also been developed in order to minimize the de-clamping problem, wherein a purposely “leaky” dielectric is utilized such that the residual charges can be discharged more quickly. For example, if the resistivity of the dielectric Rdie can be controlled to approximately 109 Ω-cm, by using Equation (1) and the above conditions, the clamping/de-clamping time can be reduced to approximately 0.0059 seconds. J-R type ESCs, for example, have been found to be effective in minimizing the de-clamping problem for bare Si wafers. However, both experiments and models indicate that a de-clamping problem is still evident for wafers having a backside insulator.
For wafers having a backside insulator, a typical de-clamping time is generally between 5 and 50 seconds, depending, at least in part, on a thickness of the backside insulator, a volume resistivity of the backside insulator, as well as surface conditions of the chuck. FIG. 1, for example, is a graph 10 illustrating a de-clamping time (RC time constant) versus thickness of the backside insulating layer for a typical J-R type ESC of the prior art. The graph 10 illustrates an exemplary gap of 1 μm (curve 15) and 4.5 μm (curve 20) between the wafer and dielectric. As can be seen, for a varying gap, when the backside insulating layer is approximately 2 kÅ, for example, the de-clamping time can generally range between approximately 4 and 20 seconds. Such large wafer de-clamping times can be costly when processing time and throughput are a concern.
Wafer de-clamping problems in J-R type ESCs are typically caused, at least in part, by charge migrating and accumulating to the backside insulator surface of the wafer. The de-clamping time can be characterized by the charging/discharging time constant, as shown in Equation (1), and the de-clamping time is typically proportional to the clamping time for the ESC. Currently, however, no acceptable solution for the de-clamping problem of J-R-type ESCs for Si wafers having a backside insulator appears to exist.
Therefore, a need exists in the art for an improved clamping and declamping system and method for J-R-type ESCs which take into account physical and electrical properties of both a semiconductor wafer having a backside insulator and the ESC.